Digital-to-analog converters (DACs) are devices that generate an analog signal from a digital signal provided thereto. DACs are used in a variety of applications including voice and video communicators, measurement and testing devices, automatic process control devices and data telemetry devices.
Two kinds of errors are encountered in the conversion of the digital signal or number to the analog signal (e.g., voltage level), namely, quantization errors and errors due to the non-ideality of the DAC. Quantization errors arise by virtue of the finite number of bits that are available to approximate the analog voltage level. The digital number is rarely more than an approximation of the real analog world made by a finite level of quantization and the errors in quantization cannot be compensated or overcome with the use of an ideal DAC.
Two characteristics (namely, resolution and accuracy) play an important role in the imperfect nature of DACs. Resolution is the smallest increment in voltage that can be discerned by the circuit and relates primarily to the number of bits of the input. For example, a 4-bit DAC has a percent resolution of 6.25% (1/16) and a 10-bit DAC has an approximate resolution of 0.1% (1/1024). Accuracy is the difference between the actual analog output and the theoretical output of a given digital word. Accuracy errors include integral and differential linearity errors. Integral non-linearity is the degree to which the analog output deviates from a straight line that extends over the full range of the waveform. Differential linearity is the difference between the deviation between the steps of a staircase waveform and the least significant bit (LSB). For instance, a differential linearity error greater than one LSB can lead to a missing code and/or non-monotonic response.
It should be noted that the two parameters, resolution and accuracy, described above are not necessarily related. For example, a DAC may have high resolution but low accuracy, and vice versa. Some applications require high resolution, but not necessarily greater accuracy. Other applications may have accuracy as the primary consideration and may disregard resolution. Sigma-delta (.SIGMA..DELTA.) data converters are one example where a DAC of high linearity but low resolution is required.
Sigma-delta (.SIGMA..DELTA.) data DACs have recently come into widespread use with the development of process technologies and the increase in digital audio and other applications. .SIGMA..DELTA. converters using oversampling (i.e., sampling at rates greater than the Nyquist rate) and quantization noise-shaping techniques demonstrate high resolution while placing modest demands on component matching and circuit performance. The .SIGMA..DELTA. converters also reduces the number of quantization levels to a minimum (i.e., two levels (one bit) or three levels). Additionally, the .SIGMA..DELTA. converters are suitable for integrated circuit technologies. High order (.gtoreq.3) single-loop DACs, for example, using one-bit (two-level) quantization can achieve more than 16-bit resolution.
The greatest strength of the one-bit .SIGMA..DELTA. converters is the inherent linearity of the one-bit internal DAC. However, one-bit .SIGMA..DELTA. converters usually require large oversampling ratios to achieve high resolution thereby placing heavy demands on the circuit operating speed and power dissipation, especially when a large portion of the power in high-resolution .SIGMA..DELTA. converters is dissipated in the digital circuitry. Additionally, one-bit .SIGMA..DELTA. converters suffer from idle-tone problems that often require dithering and high out-of-band noise that makes it difficult to design the output reconstruction filters either in the digital domain for analog-to-digital DACs or analog domain for DACs.
Multibit .SIGMA..DELTA. converters (i.e., more than two quantization levels) exhibit more robust stability characteristics with wider signal range, better immunity to idle-tone problems and lower out-of-band noise than one-bit .SIGMA..DELTA. converters. The primary drawback with multibit .SIGMA..DELTA. converters is the nonlinearity of the corresponding internal multibit DAC, which can cause increased signal distortion and noise.
The most common problem affecting linearity in DACs designed with integrated circuits (ICs) is the mismatching of the components. Mismatching occurs when two components, typically resistors or capacitors, with identical rated values are not equal. The differences in actual values are the result of deviations in the manufacturing process. Currently, pairs of resistors and capacitors may be matched to within 0.1%. This 0.1% matching of components corresponds to, approximately, a 10-bit conversion linearity. In some applications, however, a 10-bit conversion linearity is insufficient. For instance, in audio applications, a 14-bit conversion linearity may be required and, in video applications, a 12-bit conversion linearity may be required.
Traditional switched-capacitor DAC techniques include binary-weighted capacitor array, ratio-independent and self-calibrating DACs. The linearity of the binary-weighted capacitor array DAC is limited by the capacitor ratio accuracy of metal-oxide-semiconductor (MOS) technologies. Currently, with careful layout techniques, linearities of up to 11-bit can be achieved. The ratio-independent DAC requires a large gain from the operational amplifier, which can be difficult to obtain in high speed operations. The self-calibrating DAC requires extra power, chip area and more complex circuitry.
A five-level switched-capacitor DAC is described in "A 22-kHz Multibit Switched-Capacitor Sigma-delta Converter with 92 dB Dynamic Range," by Ju, et al. (Ju), IEEE Journal of Solid-State Circuits, 30(12): 1316-1324, (December 1995), which is herein incorporated by reference. Ju provides 16-bit linearity with a capacitor ratio error of 1%. While Ju discloses a DAC that achieves a high level of performance, the conversion period for the DAC requires up to three clock cycles.
Accordingly, what is needed in the art is an improved DAC that achieves shorter conversion periods and increased conversion linearities in the operation thereof.